TFTs (Thin Film Transistors) are widely used as basic electronic devices for controlling pixels of a TFT liquid crystal display (TFTLCD). FIG. 1(a) is a block diagram schematically illustrating a conventional TFTLCD. Such TFTLCD comprises an active matrix 10 and driving circuits 11. The active matrix 10 is formed on a glass substrate 1, whereas the driving circuits 11 are electrically connected to the active matrix 10 via external lines 12. Nowadays, a so-called low-temperature polysilicon thin film transistor (LTPS-TFT) technology was developed due to improved electrical properties of TFT transistors and other benefits. Please refer to FIG. 1(b). The active matrix 10 and the driving circuits 11 can be directly formed on the glass substrate 1 so as to reduce fabricating cost.
A process for producing such LTPS-TFT is illustrated with reference to FIGS. 2(a) to 2(f).
In FIG. 2(a), a polysilicon layer 21 is formed on a glass substrate 2 by laser annealing an amorphous silicon layer applied to the glass substrate 2 at a low temperature, and patterning and etching the annealed silicon layer. Then, as shown in FIG. 2(b), a photoresist 22 is formed on a selected region of the polysilicon layer 21, and an ion-implantation procedure is performed on the resulting polysilicon layer 21 with the photoresist 22 serving as a mask. By the ion-implantation procedure, B+ ions are implanted to form N-channel TFT zones. Then, a photoresist 23 is partially formed on the N-channel TFT zones, and PHx+ ions are implanted into the N-channel TFT zones with the photoresist 23 serving as a mask, thereby forming source/drain regions 24, as can be seen in FIG. 2(c). After the photoresists 22 and 23 are removed, a gate insulator 25 is formed on the resulting structure. Then, gate metal 26 (for example made of molybdenum) is formed on the gate insulator 25, as shown in FIG. 2(d). The gate metal 26 for each N-channel TFT zone has cross-sectional area less than that of the corresponding photoresist 23 for that N-channel TFT zone formed in the previous step shown in FIG. 2(c). Then, for N-channel TFT zones, lightly doped drain (LDD) regions 241 are formed by implanting P+ ions with the gate metal 26 as a mask. The N-channel TFT zones are covered with a photoresist 27, and then another ion implantation procedure is performed on the resulting structure with the photoresist 27 serving as a mask to form a P-channel TFT zone, as shown in FIG. 2(e). The dopants are B2Hx+ ions, and source/drain regions 242 are formed. Afterwards, an interlayer dielectric layer 28 and source/drain conductive lines 29 are formed in sequence, as shown in FIG. 2(f), to obtain the desired LTPS-TFT structure.
With the increasing development of integrated circuits, electronic devices have a tendency toward miniaturization. As a result of miniaturization, the channel between the source and drain regions in each TFT will become narrower and narrower. A so-called “hot electron effect” is rendered, which impairs stability of the LTPS-TFT and results in current leakage. The LDD regions are useful to reduce the hot electron effect. Conventionally, a process involving many masks and steps are involved in order to form the LDD regions. Another conventional process of forming LDD regions by a self-aligned procedure would involve reduced masking steps. For the self-aligned procedure, the LDD regions do not overlap with the gate metal 26 thereabove. It is found, however, improved device stability will be obtained when the gate metal 26 extends over the LDD region 241 to a certain extent. Unfortunately, there is likely to be parasitic capacitance occurring in the overlapped region between the gate metal 26 and the LDD region 241, which adversely causes a voltage drift of the storage capacitor and liquid crystal capacitor in a pixel cell when the pixel is turned off.